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H5RS5223CFR
512Mbit (16Mx32) GDDR3 SDRAM H5RS5223CFR
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 1.5 /Jul. 2008 1
H5RS5223CFR Revision History
Revision 0.1 0.2 0.3 Page Defined target spec. Changed tCK_max to 2ns at (-N0) & PKG drawing value 1. Revised the slew rate from 6V/ns to 3V/ns on page 54. 2. Inserted the code `C' in Part number, that means `normal power and commercial temperature'. Inserted 1.2Ghz speed bin Added IDD Values 47 43 44 44 3 48 51-52 55 Changed IDDO/IDD1/IDD5A Values Inserted the thermal characteristics table (Table 12) Inserted the note for IO reference voltage (VREF) Inserted the note (VDD/VDDQ) 1. 2. 3. 4. Inserted Inserted Inserted Inserted 1.3Ghz speed bin (-N3C) IDD Values for 1.3Ghz AC Parameter Values for 1.3Ghz Eletrical Characteristics Usage Values for 1.3Ghz History Date Oct. 2007 Oct. 2007 Nov. 2007 Remark Preliminary Preliminary Preliminary
0.4 1.0 1.1 1.2 1.3 1.4 1.5
Dec. 2007 Jan. 2008 Jan. 2008 Mar. 2008 May. 2008 Jun. 2008 Jul. 2008
Preliminary
Rev.1.5 / Jul. 2008
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H5RS5223CFR DESCRIPTION
The Hynix H5RS5223 is a high-speed CMOS, dynamic random-access memory containing 536,870,912 bits. The Hynix H5RS5223 is internally configured as a eight-bank DRAM. The Hynix H5RS5223 uses a double data rate architecture to achieve high-speed opreration. The double date rate architecture is essentially a 4n-prefetch architecture, with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the Hynix H5RS5223 consists of a 4n-bit wide, every two-clock-cycles data transfer at the internal DRAM core and two corresponding n-bit wide, one-half-clock-cycle data transfers at the I/O pins. Read and write accesses to the Hynix H5RS5223 is burst oriented; accesses start at a selected locations and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ of WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed (BA0,BA1, BA2 select the bank; A0-A11 select the row). The address bits registered coincident with the READ or WRITE command are used to select the starting column location for the burst access. Prior to normal operation, the Hynix H5RS5223 must be initialized.
FEATURES
* 2.05V/ 1.8V/ 1.5V power supply supports (For more detail, Please see the Table 12 on page 43) * * * Single ended READ Strobe (RDQS) per byte Single ended WRITE Strobe (WDQS) per byte Internal, pipelined double-data-rate (DDR) architecture; two data accesses per clock cycle * * * * * * On Die Termination Output Driver Strength adjustment by EMRS Calibrated output driver Differential clock inputs (CK and CK#) Commands entered on each positive CK edge RDQS edge-aligned with data for READ; with WDQS center-aligned with data for WRITE * 8 internal banks for concurrent operation * * * * * * * * * * * * * CAS Latency: 4~11 (clock) Data mask (DM) for masking WRITE data 4n prefetch Programmable burst lengths: 4, 8 32ms, 8K-cycle auto refresh Auto precharge option Auto Refresh and Self Refresh Modes 1.8V Pseudo Open Drain I/O Concurrent Auto Precharge support tRAS lockout support, Active Termination support Programmable Write latency(1, 2, 3, 4, 5, 6) Boundary Scan Function with SEN pin Mirror Function with MF pin
ORDERING INFORMATION
Part No. H5RS5223CFR-N3C H5RS5223CFR-N2C H5RS5223CFR-N0C H5RS5223CFR-11C H5RS5223CFR-14C H5RS5223CFR-20C H5RS5223CFR-14L H5RS5223CFR-18C VDD/VDDQ=1.5V VDD/VDDQ=1.8V VDD/VDDQ=2.05V Power Supply Clock Frequency 1300MHz 1200MHz 1000MHz 900MHz 700MHz 500MHz 700MHz 550MHz Max Data Rate 2600Mbps/pin 2400Mbps/pin 2000Mbps/pin 1800Mbps/pin 1400Mbps/pin 1000Mbps/pin 1400Mbps/pin 1100Mbps/pin POD_15 POD_18 10mmx14mm 136Ball FBGA Interface Package
Note) Above Hynix P/N's and their homogeneous Subcomponents are RoHS (& Lead free) compliant
Rev.1.5 / Jul. 2008
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H5RS5223CFR BALLOUT CONFIGURATION
1 A B C D E F G H J K L M N P R T U VDDQ VSSQ VDDQ 2 VDD DQ0 DQ2 3 VSS DQ1 DQ3 4 ZQ VSSQ VDDQ 5 6 7 8 9 MF VSSQ VDDQ 10 VSS DQ9 DQ11 11 VDD DQ8 DQ10 12 VDDQ VSSQ VDDQ
VSSQ W DQS0 RDQS0 VSSQ VDDQ VDD VSS VREF VSS VDD VSS VDD VDDQ DQ4 DQ6 VSSQ A1 NC A10 VSSQ DQ24 DQ26 DM0 DQ5 DQ7 RAS# RFU A2 DQ25 DQ27 DM3 VDDQ CAS# BA0 CKE VDDQ A0 A11 A3 VDDQ
VSSQ RDQS1 W DQS1 VSSQ VDDQ CS# BA1 W E# VDDQ A4 A7 A9 VDDQ DM1 DQ13 DQ15 BA2 CK# A6 DQ17 DQ19 DM2 DQ12 DQ14 VSSQ A5 CK A8/AP VSSQ DQ16 DQ18 VDDQ VDD VSS VREF VSS VDD VSS VDD VDDQ
VSSQ W DQS3 RDQS3 VSSQ VDDQ VSSQ VDDQ DQ28 DQ30 VDD DQ29 VDDQ DQ31 VSSQ VSS SEN
VSSQ RDQS2 W DQS2 VSSQ VDDQ VSSQ RES DQ21 DQ23 VSS DQ20 DQ22 VDD VDDQ VSSQ VDDQ
16M x 32 Configuration Refresh Count Bank Address Row Address Column Address AP Flag 2M x 32 x 8 banks 8k BA0 - BA2 A0~A11 A0~A7, A9 A8
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H5RS5223CFR
FUNCTIONAL BLOCK DIAGRAM
8Banks x 2Mbit x 32 I/O double Data Rate Synchronous DRAM
CKE CK CK# COMMAND DECODE CS# RAS# CAS# W E# CONTROL LOGIC BANK7 BANK6 BANK5 BANK4 BANK3 BANK0 BANK2 BANK1ROW ADDRESS LATCH BANK0 & ROW DECODER ADDRESS 40% LATCH & DECODER
MODE REGISTERS 15 12
REFRESH COUNTER 12 ROW ADDRESS MUX 12
BANK7 BANK6 BANK5 BANK4 BANK3 BANK2 BANK1 BANK0 MEMORY ARRAY (4096x512x128) BANK0 MEMORY ARRAY (4096x512x128) SENSE AMPLIFIERS
CCL0, CCL1 32 128 READ LATCH 32 32 32 MUX 32 DATA
CK/ CK#
DLL
DRVRS
DQ0~DQ31 SENSE AMPLIFIERS
66,536
3
INPUT REGISTERS I/O GATING DM MASK LOGIC BANK CONTROL LOGIC 128 4 4 16
512 (x128)
CK/CK#
4 4 4 4 4 32 32 32 32 32 RCVRS W DQS(0~3)
A0~A11 BA0- BA2
15
ADDRESS REGISTER 3
128 COLUMN DECODER CK/CK# 9 COLUMN ADDRESS COUNTER LATCH 7 2
W RITE FIFO & DRIVERS
MASK
4 4 32
DM(0~3)
CK OUT CK IN
32 128 DATA 32 32
COL0, COL1
4
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H5RS5223CFR
BALLOUT DESCRIPTIONS
FBGA BALLOUT J10, J11 SYMBOL CK, CK# TYPE Input DESCRIPTION Clock: CK and CK# are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of CK#. Clock Enable: CKE HIGH activates and CKE LOW deactivates the internal clock, input buffers and output drivers. Taking CKE LOW provides PRECHARGE POWER-DOWN and SELF REFRESH operations(all banks idle), or ACTIVE POWER-DOWN (row ACTIVE in any bank). CKE is synchronous for POWER-DOWN entry and exit, and for SELF REFRESH entry. CKE is asynchronous for SELF REFRESH exit and for disabling the outputs. CKE must be maintained HIGH throughout read and write accesses. Input buffers (excluding CK, CK# and CKE) are disabled during POWER-DOWN. Input buffers (excluding CKE) are disabled during SELF REFRESH. Chip Select: CS# enables (registered LOW)and disables (registered HIGH) the command decoder. All commands are masked when CS# is registered HIGH. CS# provides for external bank selection on systems with multiple banks. CS# is considered part of the command code. Command Inputs: RAS#, CAS# and WE#(along with CS#) define the command being entered. Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH along with that input data during a WRITE access. DM is sampled on rising and falling edges of WDQS. Bank Address Inputs: BA0 and BA2 define to which bank an ACTIVE, READ, WRITE or PRECHARGE command is being applied. Address Inputs: Provide the row address for ACTIVE commands, and the column address and auto precharge bit(A8) for READ/WRITE commands, to select one location out of the memory array in the respective bank. A8 sampled during a PRECHARGE command determines whether the PRECHARGE applies to one bank (A8 LOW, bank selected by BA0 - BA2 ) or all banks (A8 HIGH). The address inputs also provide the op-code during a MODE REGISTER SET command. BA0 and BA1 define which mode register (mode register or extended mode register) is loaded during the LOAD MODE REGISTER command.
H4
CKE
Input
F9
CS#
Input
H3, F4, H9
RAS#, CAS#, WE#
Input
E(3, 10), N(3, 10)
DM0-DM3
Input
G(4, 9), H10
BA0 - BA2
Input
H(2, 11), K(2-4, 9-11), L(4, 9), M(4, 9)
A0-A11
Input
B(2, 3), C(2, 3), E2, F(2, 3), G3,B(10, 11), C(10, 11), E11, F(10, 11), G10, L10, M(10, 11), N11, R(10, 11), T(10,11), L3, M(2, 3), N2,R(2, 3), T(2, 3) D(3, 10), P(3, 10) D(2, 11), P(2, 11) U4 J(2, 3)
DQ0-31
I/O
Data Input/Output:
RDQS0-3 WDQS0-3 SEN NC/RFU
Output Input Input
READ Data Strobe: Output with read data. RDQS is edge-aligned with read data. WRITE Data strobe: Input with write data. WDQS is center aligned to the input data. Scan Enable Pin. Logic High would enable Scan Mode. Should be tied to GND when not in use. This pin is a CMOS input. No Connect
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H5RS5223CFR BALLOUT DESCRIPTIONS
FBGA Ball Out A(1, 12), C(1, 4, 9, 12), J(4, 9), N(1, 4, 9, 12), R(1, 4, 9, 12), U(1, 12) B(1, 4, 9, 12), D(1, 4, 9, 12), G(2, 11), L(2, 11), P(1, 4, 9, 12), T(1, 4, 9, 12) A(2, 11), F(1, 12), M(1, 12), U(2, 11) K(1, 12) A(3, 10), G(1, 12), L(1, 12), U(3, 10) J(1, 12) H(1, 12) A9 A4 U9 SYMBOL VDDQ TYPE Supply DESCRIPTION DQ Power Supply: +1.8V. Isolated on the die for improved noise immunity. DQ Ground: Isolated on the die for improved noise immunity. Power Supply: +1.8V. Ground Reference voltage. Mirror Function for clamshell mounting of DRAMs External Reference Pin for autocalibration. It should be connected to RQ(=240) Reset Pin. The RES pin is a VDD CMOS input.
-CONTINUE
VSSQ VDD VSS VREF MF ZQ RES
Supply Supply Supply Supply Reference Reference Reference
Mirror Function
The GDDR3 SDRAM provides a mirror function(MF) ball to change the physical location of the control lines and all address lines, assisting in routing devices back to back. The MF ball will affect RAS#, CAS#, WE#, CS# and CKE on balls H3, F4, H9, F9 and H4 respectively and A0, A1, A2, A3, A4, A5, A6, A7, A8, A9, A10, A11, BA0, BA1 and BA2 on balls K4, H2, K3, M4, K9, H11, K10, L9, K11, M9, K2, L4, G4, G9 and H10 respectively and only detects a DC input. The MF ball should be tied directly to VSS of VDD depending on the control line orientation desired. When MF ball is tied low the ball orientation is as follows. RAS#-H3, CAS#-F4, WE#-H9, CS#-F9, CKE-H4, A0-K4, A1-H2, A2-K3, A3M4, A4-K9, A5-H11, A6-K10, A7-L9, A8-K11, A9-M9, A10-K2, A11-L4, BA0-G4, BA1-G9 and BA2-H10. The high condition on the MF ball will change the location of the control balls as follows; CS#-F4, cas#-F9, ras#-H10, WE#-H4, CKE-H9, A0-K9, A1-H11, A2-K10, A3-M9, A4-K4, A5-H2, A6-K3, A7-L4, A8-K2, A9-M4, A10-K11, A11-L9, BA0-G9, BA1-G4 and BA2-H3. This Mirror Fuction does not work under Boundary Scan Test condition.
Mirror Function Signal Mapping
PIN RAS# CAS# WE# CS# CKE A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 BA0 BA1 BA2 MF LOGIC STATE HIGH H10 F9 H4 F4 H9 K9 H11 K10 M9 K4 H2 K3 L4 K2 M4 K11 L9 G9 G4 H3 LOW H3 F4 H9 F9 H4 K4 H2 K3 M4 K9 H11 K10 L9 K11 M9 K2 L4 G4 G9 H10
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H5RS5223CFR GDDR3 Initialization and Power Up
GDDR3 SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in undefined operation. Power must be first applied to VDD and VDDQ simultaneously or VDD first and VDDQ later, and then to VREF. VREF can be applied any time after VDDQ. Once power has been applied and the clocks are stable the GDDR3 device requires 200us before the RES pin transitions to high. Upon power-up and after the clock is stable, the on-die termination value for the address and control pins will be set, based on the state of CKE when the RES pin transitions from LOW to HIGH. On the rising edge of RES, the CKE pin is latched to determine the on die termination value for the address and control lines. If CKE is sampled at a logic LOW then the on die termination will be set to 1/2 of ZQ and, if CKE is sampled logic HIGH then the on die termination will be set to the same value as ZQ. CKE must meet tATS and tATH on the rising of RES to set the on die termination for address and control lines. Once tATH is met, set CKE to HIGH. An additional 200us is required for the address and command on die terminations to calibrate and update. RES must be maintained at a logic LOW-level value and CS# must be maintained HIGH, during the first stage of power-up to ensure that the DQ outputs will be in a High-Z state(un-terminated). After the RES pin transitions from LOW to HIGH, wait until a 200us delay is satisfied. Issue DESELECT on the command bus during this time. Issue a PRECHARGE ALL command. Next a LOAD MODE REGISTER command must be issued for the extended mode register (BA1 LOW and BA0 HIGH) to activate the DLL and set operating parameters, followed by the LOAD MODE REGISTER command (BA0/BA1 both LOW) to reset the DLL and to program the rest of the operating parameters. 5k clock cycles are required between the DLL reset and any READ command to allow the DLL to lock. A PRECHARGE ALL command should then be applied, placing the device in the all banks idle state. Once in the idle state, two AUTO REFRESH cycles must be issued. Following these requirements, the GDDR3 SDRAM is ready for normal operation.
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H5RS5223CFR
ODT Updating
The GDDR3 SDRAM uses programmable impedance output buffers. This allows a user to match the driver impedance to the system. To adjust the impedance, an external precision resistor (RQ) is connected between the ZQ pin and VSSQ. The value of the resistor must be six times the desired driver impedance. For example, a 240. resistor is required for an output impedance of 40. To ensure that output impedance is one-sixth the value of RQ (within 10 percent), RQ should be in the range of 210. to 270. (30. - 50. output impedance). CK and CK# are not internally terminated. CK and CK# will be terminated on the system module using external 1% resistors. The output impedance and on die termination is updated during every AUTO REFRRESH commands to compensate for variations in supply voltage and temperature. The output impedance updates are transparent to the system. Impedance updates do not affect device operation, and all datasheet timings and current specifications are met during an update. A maximum of eight AUTO REFRESH commands can be posted to any given GDDR3 SDRAM, meaning that the maximum absolute interval between any AUTO REFRESH command and the next AUTO REFRESH command is 8 x 3.9us (31.2us). This maximum absolute interval guarantees that the output drivers and the on die terminations of GDDR3 SDRAMs are recalibrated often enough to keep the impedance characteristics of those within the specified boundaries.
ODT Control
Bus snooping for READ commands other than CS# is used to control the on die termination in the dual load configuration. The GDDR3 SGRAM will disable the DQ and RDQS on die termination when a READ command is detected regardless of the state of CS#. The on die termination is disabled x clocks after the READ command where x equals CL-1 and stay off for a duration of BL/2+2CK. In a two-rank system, both DRAM devices snoop the bus for READ commands to either device and both will disable the on die termination, for the DQ and DQS pins if a READ command is detected. The on die termination for all other pins on the device is always turned-on for both a single-rank system and a dual-rank system unless it is turned off in the EMRS. Only DQ,WDQS and DM pins can turn off through the EMRS.
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H5RS5223CFR Mode Register Definition
The mode register is used to define the specific mode of operation of the GDDR3 SDRAM. This definition includes the selection of a burst length, CAS latency, WRITE latency, and operating mode, as shown in Figure 3, Mode Register Definition, on page 11. The mode register is programmed via the MODE REGISTER SET command (with BA0=0, BA1=0 and BA2=0) and will retain the stored information until it is programmed again or the device loses power (except for bit A8, which is self-clearing). Re-programming the mode register will not alter the contents of the memory. The mode register must be loaded (reloaded) when all banks are idle and no bursts are in progress, and the controller must wait the specified time before initiating any subsequent operation. Violating either of these requirements will result in unspecified operation. Mode register bits A2-A0 specify the burst length; A3 specifies the type of burst (sequential); A4-A6 specify the CAS latency; A7 is a test mode; A8 specifies the operating mode; and A9-A11 specifiy the WRITE latency.
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H5RS5223CFR Figure 3: Mode Register Definition
BA1 0 BA0 0 A11 A10 WL A9 A8 DR A7 TM A6 A5 A4 A3 BT A2 CL A1 A0
CAS Latency
Burst Length
A8 0 1
DLL Reset No Yes
A3 0 1
Burst Type Sequential Reserved
A1 A7 0 1 Test Mode Normal Yes 0 0 1 1
A0 0 1 0 1
Burst Length Reserved Reserved 4 8
A11 0 0 0 0 1 1 1 1
A10 0 0 1 1 0 0 1 1
A9 0 1 0 1 0 1 0 1
WRITE Latency Reserved 1 2 3 4 5 6 Reserved
A2 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1
A6 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
A5 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
A4 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
CAS Latency 8 9 10 11 4 5 6 7 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Note: 1) The DLL reset command is self-clearing.
1
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H5RS5223CFR Burst Length
Read and write accesses to the GDDR3 SDRAM are burst-oriented, with the burst length being programmable, as shown in Figure3, Mode Register Definition. The burst length determines the maximum number of column locations that can be accessed for a given READ or WRITE command. Burst lengths of 4 or 8 locations are available for the sequential burst type. Reserved states should not be used, as unknown operation or incompatibility with future versions may result. When a READ or WRITE command is issued, a block of columns equal to the burst length is effectively selected. All accesses for that burst take place within this block, meaning that the burst will wrap within the block if a boundary is reached. The block is uniquely selected by A2. Ai when the burst length is set to four and by A3. Ai when the burst length is set to eight(where Ai is the most significant column address bit for a given configuration). The remaining(least significant) address bit(s) is (are) used to select the starting location within the block. The programmed burst length applies to both read and write bursts.
Burst Type
Accesses within a given burst must be programmed to be sequential; this is referred to as the burst type and is selected via bit A3. This device does not support the interleaved burst mode found in DDR SDRAM devices. The ordering of accesses within a burst is determined by the burst length, the burst type, and the starting column address, as shown in Table3.
Table 3: Burst Definition
Burst1, 2 Length Starting Column Address Order of Accesses Within a Burst Type=Sequential A1 0 A2 8 0 1 A1 0 0 A0 0 A0 0 0 0-1-2-3-4-5-6-7 4-5-6-7-0-1-2-3 0-1-2-3
4
NOTE: 1. For a burst length of four, A2-A7 select the block of four burst; A0-A1 select the starting column within the block and must be set to zero. 2. For a burst length of eight, A3-A7 select the of eight burst; A0-A2 select the starting column within the block.
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H5RS5223CFR CAS Latency
The CAS latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first bit of output data. The latency can be set to 7 1 clocks, as shown in Figure 4, CAS Latency, on page 13. If a READ command is registered at
clock edge n, and the latency is m clocks, the data will be available nominally coincident with clock edge n + m. Table4 indicates the operating frequencies at which each CAS latency setting can be used. For the proper operation, do not change the CL without DLL reset. Or proper CL should be set with DLL reset code Reserved states should not be used as unknown operation or incompatibility with future versions may result.
Table 4: CAS Latency
ALLOWABLE OPERATING FREQUENCY (MHz) SPEED -N3 -N2 -N0 -11 -14(L) -18 -20 CL=11 <=1300 <=1200 <=1000 <=900 <=700 <=550 <=500 CL=10 CL=9 CL=7
Figure 4: CAS Latency
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H5RS5223CFR Write Latency
The WRITE latency (WL) is the delay, in clock cycles,between the registration of a WRITE command and the availability of the first bit of input data as shown in Figure5. The latency can be set from 1 to 6 clocks depending on the operating frequency and desired current draw. When the write latencies are set to 1 or 4 clocks, the input receivers never turn off, in turn, raising the operating power. When the WRITE latency is set to 5 or 6 clocks the input receivers turn on when the WRITE command is registered. If a WRITE command is registered at clock edge n, and the latency is m clocks, the data will be available nominally coincident with clock edge n + m. Reserved states should not be used as unknown operation or incompatibility with future versions may result.
Figure 5: WRITE Latency
Test Mode
The normal operating mode is selected by issuing a MODE REGISTER SET command with bit A7 set to zero, and bits A0~A6 and A8~A11 set to the desired values. Test Mode is initiated by issuing a MODE REGISTER SET command with bit A7 set to one, and bits A0~A6 and A8~A11 set to the desired values. Test mode funtions are specific to each DRAM vendor and their exact function are hidden from the user.
DLL Reset
The normal operating mode is selected by issuing a MODE REGISTER SET command with bit A8 set to zero, and bits A0~A7 and A9~A11 set to the desired values. A DLL reset is initiated by issuing a MODE REGISTER SET command with bit A8 set to one, and bits A0~A7 and A9~A11 set to the desired values. When a DLL Reset is complete the GDDR3 SDRAM Reset bit, A8 of the mode register is self clearing (i.e.automatically set to a zero by the DRAM). Test modes and reserved states should not be used because unknown operation or incompatibility with future versions may result.
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H5RS5223CFR Extended Mode Register
The extended mode register controls functions beyond those controlled by the mode register; these additional functions are DLL enable/disable, drive strength, data termination, vendor ID. These functions are controlled via the bits shown in Figure 6, Extended Mode Register Definition. The extended mode register is programmed via the LOAD MODE REGISTER command to the mode register (with BA0 = 1, BA1 = 0 and BA2=0) and will retain the stored information until it is programmed again or the device loses power. The enabling of the DLL should always be followed by a LOAD MODE REGISTER command to the mode register (BA0/BA1 both low) to reset the DLL.The extended mode register must be loaded when all banks are idle and no bursts are in progress, and the controller must wait the specified time before initiating any subsequent operation. Violating either of these requirements could result in unspecified operation.
Figure 6: Extended Mode Register Definition
BA1 0 BA0 1 A11 Term A10 VID A9 Ron A8 0 A7 tWR A6 DLL A5 A4 tWR A3 DT A2 A1 DZ A0
Ron of Pull-up
A9 0 1
Ron 40 60
A1 A6 0 1 DLL enable Enable Disable 0 0 1 1
A0 0 1 0 1
Drive Strength Auto Cal 30 40 50(48)
A10 0 1
Vendor ID Off On A7 A5 0 0 1 1 0 0 1 1 A4 0 1 0 1 0 1 0 1 tWR 12 14 5 6 7 8 9 10
A3 0 0 1 1
A2 0 1 0 1
Data Termination DT disabled RES 1/4 RQ 1/2 RQ
A11 0 1
C/A Termination Default Half of default
0 0 0 0 1 1 1 1
NOTE: 1. The DT disable function disables all pins. 2. The default setting at Power Up for A3,A2 is 10 or 11 3. If the user activates bits in the extended mode register in an optional field, device will work improperly. 4. The optional values of the drive strength (A1,A0) are only targets and can be determined by the DRAM vendor. 5. WR_A (write recovery time for autoprecharge) in clock cycles is calculated by dividing tWR (in nS) and rounding up to the next integer (WR[cycles] = tWR(ns)/tCK(ns)). The mode register must be programmed to this value. 6. Default value in C/A Termination is determined by CKE status at the rising edge of RESET during power-up.
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H5RS5223CFR DLL Enable/Disable
The DLL must be enabled for normal operation. DLL enable is required during power-up initialization and upon returning to normal operation after disabling the DLL for debugging or evaluation. (When the device exits self refresh mode, the DLL is enabled automatically.) Any time the DLL is enabled, 5K clock cycles must occur before a READ command can be issued.
tWR(WR_A)
The value of tWR in the AC parametrics table on page 49 of this specification is loaded into register bits 5 and 4. The WR_A (write recovery time for autoprecharge) in clock cycles is calculated by dividing tWR (in ns) and rounding up to the next integer (WR[cycles] = tWR(ns)/tCK(ns)). The mode register must be programmed to this value.
Data Termination
The data termination value is used to define the value for the on die termination for the DQ, DM, and WDQS pins. The GDDR3 device supports one-quarter ZQ and one-half ZQ termination for a nominal 60 for a single- or dual-loaded system. or 120 set with bit A3 and A2 during an EMRS command
Data Driver Impedance
The Data Driver Impedance, DZ, is used to determine the value of the data drivers impedance. When auto calibration is used the data driver impedance is set to 1/6 ZQ and it's tolerance is determined by the calibration accuracy of the device. When any other value is selected the target impedance is set nominally to the selected impedance. However, the accuracy is now determined by the device's specific process corner, applied voltage and operating temperature.
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H5RS5223CFR Manufacturers Vendor Code Identification
The Manufacturers Vendor Code, V, is selected by issuing an EXTENDED MODE REGISTER SET command with bits A10 set to 1, and bits A0-A9 and A11 set to the desired values. When the V function is enabled the GDDR3 SDRAM will provide its manufacturers vendor code on DQ[3:0] and revision identification on DQ[7:4]. The code will be driven onto the DQ bus after tIDON with respect to the EMRS that set A10 to 1. The DQ bus will be continuously driven until an EMRS write sets A10 back to 0. The DQ bus will be in a Hi-Z state after tIDOFF. The code can be sampled by the controller after waiting tIDON max and before tIDOFF min.
Table 5: Vendor IDs
VENDOR Reserved Samsung Infineon Elpida Etron Nanya DQ(3:0) 0 1 2 3 4 5
Hynix
Mosel Winbond ESMT Reserved Reserved Reserved Reserved Reserved Micron
6
7 8 9 A B C D E F
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H5RS5223CFR Clock frequency change sequence during the device operation Not only Clock frequency but also VDD change sequence as below
Both existing tCK and desired tCK are in DLL-On mode - Change frequency from existing frequency to desired frequency - Issue Precharge All Banks command - Issue MRS command to reset the DLL while other fields are valid and required 5K tCK to lock the DLL - Issue Precharge All Banks command. Issue at least Auto-Refresh command
Existing tCK is in DLL-on mode while desired tCK is in DLL-off mode Issue Precharge All Banks command Issue EMRS command to disable the DLL Issue Precharge All Banks command Change the frequency from existing to desired. Issue Auto-Refresh command at least two. Issue MRS command
Clock frequency change in case existing tCK is in DLL-off mode while desired tCK is in DLL-on mode - Issue Precharge All Banks command and issue EMRS command to disable the DLL. - Issue Precharge All Banks command. - Change the clock frequency from existing to desired - Issue Precharge All Banks command. - Issue EMRS command to enable the DLL - Issue MRS command to reset the DLL and required 5K tCK to lock the DLL. - Issue Precharge All Banks command. - Issue Auto-Refresh command at least two
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H5RS5223CFR Commands
Table6 provides a quick reference of available commands, followed by a description of each command. Two additional truth tables appear following the Operation section; these tables provide current state/next state information.
Table 6: Truth Table - Commands
Note: 1 NAME (FUNCTION) DESELECT (NOP) NO OPERATION (NOP) ACTIVE (Select bank and activate row) READ (Select bank and column, and start READ burst) WRITE (Select bank and column, and start WRITE burst) PRECHARGE (Deactivate row in bank or banks) AUTO REFRESH or SELF REFRESH (Enter self refresh mode) LOAD MODE REGISTER DATA TERMINATOR DISABLE CS# H L L L L L L L X RAS# X H L H H L L L H CAS# X H H L L H L L L WE# X H H H L L H L H ADDR X X Bank/Row Bank/Col Bank/Col Code X Op-Code X NOTES 8 8 3 4 4 5 6, 7 2 10
Table 7: Truth Table 2 - DM Operation
NAME (FUNCTION) Write Enable Write Inhibit DM L H DQS Valid X NOTES 9 8
NOTE: 1. CKE is HIGH for all commands shown except SELF REFRESH. 2. BA0-BA1 select either the mode register or the extended mode register (BA0 = 0, BA1 = 0 select the mode register; BA0 = 1, BA1 = 0 select extended mode register; other combinations of BA0.BA1 are reserved). A0-A11 provide the opcode to be written to the selected mode register. 3. BA0-BA2 provide bank address and A0-A11 provide row address. 4. BA0-BA2 provide bank address; A0-A7 and A9 provide column address; A8 HIGH enables the auto precharge feature (non-persistent), and A8 LOW disables the auto precharge feature. 5. A8 LOW: BA0-BA2 determine which bank is precharged. A8 HIGH: all banks are precharged and BA0-BA2 are "Don't Care." 6. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW. 7. Internal refresh counter controls row addressing; all inputs and I/Os are Don't Care except for CKE. 8. DESELECT and NOP are functionally interchangeable. 9. Used to mask write data; provided coincident with the corresponding data. 10. Used for bus snooping when the DQ termination is set to 120 ohms in the EMR and cannot be used during power-down or self refresh.
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H5RS5223CFR Deselect
The DESELECT function (CS# HIGH) prevents new commands from being executed by the GDDR3 SDRAM. The GDDR3 SDRAM is effectively deselected. Operations already in progress are not affected.
NO Operation (NOP)
The NO OPERATION (NOP) command is used to instruct the selected GDDR3 SDRAM to perform a NOP(CS# LOW). This prevents unwanted commands from being registered during idle or wait states. Operations already in progress are not affected.
LOAD MODE REGISTER
The mode registers are loaded via inputs A0~A11. See mode register descriptions in the Register Definition section. The LOAD MODE REGISTER command can only be issued when all banks are idle, and a subsequent executable command cannot be issued until tMRD is met.
ACTIVE
The ACTIVE command is used to open (or activate) a row in a particular bank for a subsequent access. The value on the BA0~BA2 inputs selects the bank, and the address provided on inputs A0~A11 selects the row. This row remains active (or open) for accesses until a precharge command is issued to that bank. A precharge command must be issued before opening a different row in the same bank.
READ
The READ command is used to initiate a burst read access to an active row. The value on the BA0~BA2 inputs selects the bank, and the address provided on inputs A0~A7, A9 selects the starting column location. The value on input A8 determines whether or not auto precharge is used. If auto precharge is selected, the row being accessed will be precharged at the end of the read burst; if auto precharge is not selected, the row will remain open for subsequent accesses.
WRITE
The WRITE command is used to initiate a burst write access to an active row. The value on the BA0~BA2 inputs selects the bank, and the address provided on inputs A0~A7, A9 selects the starting column location. The value on input A8 determines whether or not auto precharge is used. If auto precharge is selected, the row being accessed will be precharged at the end of the write burst; if auto precharge is not selected, the row will remain open for subsequent accesses. Input data appearing on the DQs is written to the memory array subject to the DM input logic level appearing coincident with the data. If a given DM signal is registered LOW, the corresponding data will be written to memory; if the DM signal is registered HIGH, the corresponding data inputs will be ignored and a write will not be executed to that byte/column location.
PRECHARGE
The PRECHARGE command is used to deactivate the open row in a particular bank or the open row in all banks. The bank(s) will be available for a subsequent row access a specified time (tRP) after the precharge command is issued. Input A8 determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged, inputs BA0.BA2 select the bank. Otherwise, BA0. BA2 are treated as "Don't Care." Once a bank has been precharged, it is in the idle state and must be activated prior to any READ or WRITE commands being issued to that bank. A PRECHARGE command will be treated as a NOP if there is no open row in that bank (idle state) or if the previously open row is already in the process of precharging.
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H5RS5223CFR Auto Precharge
Auto precharge is a feature that performs the same individual-bank precharge function described above but without requiring an explicit command. This is accomplished by using A8 to enable auto precharge in conjunction with a specific READ or WRITE command. A precharge of the bank/row that is addressed with the READ or WRITE command is automatically performed upon completion of the READ or WRITE burst. Auto precharge is nonpersistent in that it is either enabled or disabled for each individual Read or Write command. Auto precharge ensures that the precharge is initiated at the earliest valid stage within a burst. This "earliest valid stage" is determined as if an explicit PRECHARGE command was issued at the earliest possible time, without violating tRAS min, as described for each burst type in the Operation section of this data sheet. The user must not issue another command to the same bank until the precharge time (tRP) is completed.
AUTO REFRESH
The addressing is generated by the internal refresh controller. This makes the address bits a Don't Care during an AUTO REFRESH command. The 512Mb x32 GDDR3 SDRAM requires AUTO REFRESH cycles at an average interval of 3.9us (maximum). A maximum of eight AUTO REFRESH commands can be posted to any given GDDR3 SDRAM, meaning that the maximum absolute interval between any AUTO REFRESH command and the next AUTO REFRESH command is 9 x 3.9us (35.1us). This maximum absolute interval allows GDDR3 SDRAM output drivers to automatically recalibrate to compensate for voltage and temperature changes. AUTO REFRESH is used during normal operation of the GDDR3 SDRAM and is analogous to CAS#-BEFORE-RAS# (CBR) refresh in FPM/EDO DRAMs.This command is nonpersistent, so it must be issued each time a refresh is required.
SELF REFRESH
The SELF REFRESH command can be used to retain data in the GDDR3 SDRAM, even if the rest of the system is powered down. When in the self refresh mode, the GDDR3 SDRAM retains data without external clocking. The SELF REFRESH command is initiated like an AUTO REFRESH command except CKE is disabled(LOW). The DLL is automatically disabled upon entering SELF REFRESH and is automatically enabled and reset upon exiting SELF REFRESH. The on-die termination is also disabled upon entering Self Refresh except for CKE and enabled upon exiting Self Refresh. (5K clock cycles must then occur before a READ command can be issued). Input signals except CKE are "Don't Care" during SELF REFRESH. The procedure for exiting self refresh requires a sequence of commands. First, CK and CK# must be stable prior to CKE going back HIGH. Once CKE is HIGH, the GDDR3 SDRAM must have NOP commands issued for tXSNR because time is required for the completion of any internal refresh in progress. A simple algorithm for meeting both refresh and DLL requirements and output calibration is to apply NOPs for 1000 clock cycles before applying any other command to allow the DLL to lock and the output drivers to recalibrate. If the GDDR3 device enters SELF REFRESH with the DLL disabled the GDDR3 device will exit SELF REFRESH with the DLL disabled.
DATA TERMINATOR DISABLE (BUS SNOOPING FOR READ COMMANDS)
Bus snooping for READ commands other than CS# is used to control the on-die termination in the dual load configuration. The GDDR3 SDRAM will disable the on-die termination when a READ command is detected, regardless of the state of CS#, when the ODT for the DQ pins are set for dual loads (120 ).The on-die termination is disabled x clocks after the READ command where x equals CL-1 and stay off for a duration of BL/2 +2CK, as shown in Figure8, Data Termination Disable Timing on page15. In a two-rank system, both DRAM devices snoop the bus for READ commands to either device and both will disable the on-die termination if a READ command is detected. The on-die termination for all other pins on the device are always turned-on for both a single-rank system and a dual-rank system.
Boundary Scan Test Mode
The 512Mb GDDR3 incorporates a modified boundary scan test mode as an optional feature. This mode doesn't operate in accordance with IEEE Standard 1149.11990. To save the current GDDR3 ballout, this mode will scan the parallel data input and output the scanned data through WDQS0 pin controlled by an addon pin, SEN which is located at U4 of 136 ball package. You can find the detailed descriptions of this feature on Appendix C (page 62).
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H5RS5223CFR Figure 8: Data Termination Disable Timing
NOTE: 1. DO n = data-out from column n. 2. Burst length = 4. 3. Three subsequent elements of data-out appear in the specified order following DO n. 4. Shown with nominal tAC and tDQSQ. 5. RDQS will start driving high one-half clock cycle prior to the first falling edge. 6. The Data Terminators are disabled starting at CL - 1 and the duration is BL/2 + 2CK. 7. READS to either rank disable both ranks' termination regardless of the logic level of CS#.
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H5RS5223CFR Operations
Bank/Row Activation
Before any READ or WRITE commands can be issued to a bank within the GDDR3 device, a row in that bank must be "opened." This is accomplished via the ACTIVE command, which selects both the bank and the row to be activated, as shown in Figure 9, Activating a Specific Row in a Specific Bank. After a row is opened with an ACTIVE command, a READ or WRITE command may be issued to that row, subject to the tRCD specification. tRCD min should be divided by the clock period and rounded up to the next whole number to determine the earliest clock edge after the ACTIVE command on which a READ or WRITE command can be entered. For example, a tRCD specification of 15ns with a 550 MHz clock(1.8ns period) results in 7.5 clocks rounded to 8. This is reflected in Figure 10, Example: Meeting tRCD, which overs any cases where 7 < tRCDMIN/tCK <= 8. The same procedure is used to convert other specification limits from time units to clock cycles. A subsequent ACTIVE command to a different row in the same bank can only be issued after the previous active row has been closed (precharged). The minimum time interval between successive ACTIVE commands to the same bank is defined by tRC. A subsequent ACTIVE command to another bank can be issued while the first bank is being accessed,which results in a reduction of total row-access overhead. The minimum time interval between successive ACTIVE commands to different banks is defined by tRRD.
Figure 9: Activating a Specific Row in a Specific Bank
Figure 10: Example: Meeting tRCD
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H5RS5223CFR READ Timing
READ burst is initiated with a READ command.
The starting column and bank addresses are provided with the READ command and auto precharge is either enabled or disabled for that burst access with the A8 pin. If auto precharge is enabled, the row being accessed is precharged at the completion of the burst after tRAS min has been met.
During READ bursts, the first valid data-out element from the starting column address will be available following the CAS latency after the READ command. Each subsequent data-out element will be valid nominally at the next positive or negative RDQS edges. The GDDR3 SDRAM drives the output data edge aligned to RDQS. And all outputs, i.e. DQs and RDQS, are also edge aligned to the clock. Prior to the first valid RDQS rising edge, a cycle is driven and specified as the READ preamble. The preamble consists of a half cycle High followed by a half cycle Low driven by the GDDR3 SDRAM. The cycle on RDQS consisting of a half cycle Low coincident with the last data-out element followed by a half cycle High is known as the read postamble, and it will be driven by the SDRAM. The SDRAM toggles RDQS only when it is driving valid data out onto on the bus. Upon completion of a burst, assuming no other command has been initiated; the DQs and RDQS will go to be in Hi-Z state. VDDQ due to the on die termination. long as the bus turn around time is met. READ data cannot be terminated or truncated. A PRECHARGE can also be issued to the SDRAM with the same timing restriction as the new READ command if tRAS is met as shown in Figure 17, READ to Precharge, on page 29. A WRITE can be issued any time after a READ command as long as the bus turn around time is met as shown in Figure 16, READ to WRITE, on page 28. READ data cannot be terminated or truncated
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H5RS5223CFR Figure 12: READ Burst
NOTE: 1. DO n = data-out from column n. 2. Burst length = 4. 3. Three subsequent elements of data-out appear in the specified order following DO n. 4. Shown with nominal tAC and tDQSQ. 5. RDQS will start driving high one-half clock cycle prior to the first falling edge.
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H5RS5223CFR Figure 13: Consecutive READ Bursts
NOTE: 1. DO n (or b) = data-out from column n (or column b). 2. Burst length = 4 3. Three subsequent elements of data-out appear in the programmed order following DO n. 4. Three subsequent elements of data-out appear in the programmed order following DO b. 5. Shown with nominal tAC, and tDQSQ. 6. Example applies only when READ commands are issued to same device. 7. RDQS will start driving high one half clock cycle prior to the first falling edge of RDQS.
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H5RS5223CFR Figure 14: Non-Consecutive READ Bursts
NOTE: 1. DO n (or b) = data-out from column n (or column b). 2. Burst length = 4. 3. Three subsequent elements of data-out appear in the programmed order following DO n. 4. Three subsequent elements of data-out appear in the programmed order following DO b. 5. Shown with nominal tAC and tDQSQ. 6. Example applies when READ commands are issued to different devices or nonconsecutive READs. 7. RDQS will start driving high one-half clock cycle prior to the first falling edge of RDQS.
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H5RS5223CFR Figure 15: Random Read Accesses
NOTE: 1. DO n (or x or b or g) = data-out from column n (or column x or column b or column g). 2. Burst length = 4. 3. READs are to an active row in any banks. 4. Shown with nominal tAC and tDQSQ. 5. RDQS will start driving high one-half clock cycle prior to the first falling edge of RDQS.
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H5RS5223CFR Figure 16: Read to Write
T0 CK# CK CMD ADD RDQS WDQS DQ ODT
ODT On
DQn DI b
T7
T8
T9
T10
T11
T12
READ
NOP
WRITE
NOP
NOP
NOP
NOP
Bank Col n
Bank Col b
CL=7
WL=3
On-Die Termination Off
On-Die Termination On
CL=7, BL=4, WL=3
NOTE: 1. DQ n = Data-out from column n. 2. DI b = Data-in from column b. 3. Shown with nominal tAC, tDQSQ and tDQSS. 4. Read Preamble consists of a half cycle High followed by a half cycle Low driven by device 5. Write Data cannot be driven onto the DQ bus for 2 clocks after the READ data is off the bus. 6. The timing diagram covers a READ to a WRITE command from different device, different bank or the same row in the same bank.
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H5RS5223CFR Figure 17: READ to Precharge
NOTE: 1. DO n = data-out from column n. 2. Burst length = 4. 3. Three subsequent elements of data-out appear in the programmed order following DO n. 4. Shown with nominal tAC and tDQSQ. 5. READ to PRECHARGE equals two clocks, which enables two data pairs of data-out. 6. PRE = PRECHARGE command; ACT = ACTIVE command. 7. RDQS will start driving high one-half clock cycle prior to the first falling edge of RDQS.
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H5RS5223CFR WRITE Timing
WRITE burst is initiated with a WRITE command.
The starting column and bank addresses are provided with the WRITE command, and auto precharge is either enabled or disabled for that access with the A8 pin. If auto precharge is enabled, the row being accessed is precharged at the completion of the burst.
During WRITE bursts, the first valid data-in element will be registered on the rising edge of WDQS following the write latency set in the mode register and subsequent data elements will be registered on successive edges of WDQS. Prior to the first valid WDQS rising edge, a cycle is needed and specified as the WRITE Preamble. The preamble consists of a half cycle High followed by a half cycle Low driven by the controller. The cycle on WDQS following the last data-in element is known as the write postamble and must be driven High by the controller, it can not be left to float High using the on die termination. The WDQS should only toggle on data transfers.
The time between the WRITE command and the first valid rising edge of WDQS (tDQSS) is specified relative to the write latency (WL - 0.25tCK and WL + 0.25tCK). All of the WRITE diagrams show the nominal case, and where the two extreme cases (i.e., tDQSS [MIN] and tDQSS [MAX]) might not be intuitive, they have also been included. Upon completion of a burst, assuming no other command has been initiated, the DQs should remain Hi-Z and any additional input data will be ignored.
Data for any WRITE burst may not be truncated with any subsequent command. A subsequent WRITE command can be issued on any positive edge of clock following the previous WRITE command assuming the previous burst has completed. The subsequent WRITE command can be issued x cycles after the previous WRITE command, where x equals the number of desired nibbles x2 (nibbles are required by 4n-prefetch architecture) i.e. BL/2. A subsequent READ command can be issued once tWTR is met or a subsequent PRECHARGE command can be issued once tWR is met. After the PRECHARGE command, a subsequent command to the same bank cannot be issued until tRP is met.
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H5RS5223CFR Figure 19: WRITE Burst
NOTE: 1. DI b = data-in for column b. 2. Three subsequent elements of data-in are applied in the specified order following DI b. 3. A burst of 4 is shown. 4. A8 is LOW with the WRITE command (auto precharge is disabled). 5. Write latency is set to 4.
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H5RS5223CFR Figure 20: Consecutive WRITE to WRITE
NOTE: 1. DI b, etc. = data-in for column b, etc. 2. Three subsequent elements of data-in are applied in the specified order following DI b. 3. Three subsequent elements of data-in are applied in the specified order following DI n. 4. Burst of 4 is shown. 5. Each WRITE command may be to any bank of the same device. 6. WRITE latency is set to 3.
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H5RS5223CFR Figure 21: NonConsecutive WRITE to WRITE
NOTE: 1. DI b, etc. = data-in for column b, etc. 2. Three subsequent elements of data-in are applied in the specified order following DI b. 3. Three subsequent elements of data-in are applied in the specified order following DI n. 4. A burst of 4 is shown. 5. Each WRITE command may be to any banks. 6. WRITE latency set to 3.
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H5RS5223CFR Figure 22: Random WRITE Cycles
NOTE: 1. DI b, etc. = data-in for column b, etc. 2. b', etc. = the next data-in following DI b, etc., according to the specified burst order. 3. Programmed burst length = 4 case is shown. 4. Each WRITE command may be to any banks. 5. Last write command will have the rest of the nibble on T8 and T8n. 6. WRITE latency is set to 3.
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H5RS5223CFR Figure 23: WRITE to READ Timing
NOTE: 1. DI b = Data In for column b 2. Three subsequent elements of Data In are applied following D1 b 3. tWTR is referenced from the first positive CK edge after the last Data In 4. The READ and WRITE commands may be to any bank. 5. WRITE Latency is set to 1 6. The 4n prefetch architecture requires a 2-clock WRITE-to-READ turn around time (tWTR).
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H5RS5223CFR Figure 24: WRITE to PRECHARGE
NOTE: 1. DI b = data-in for column b. 2. Three subsequent elements of data-in are applied in the specified order following DI b. 3. A burst of 4 is shown. 4. A8 is LOW with the WRITE command (auto precharge is disabled). 5. WRITE latency is set to 3.
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H5RS5223CFR PRECHARGE
The PRECHARGE command (shown in Figure25) issused to deactivate the open row in a particular bank or the open row in all banks. The bank(s) will be available for a subsequent row access some specified time (tRP) after the precharge command is issued. Input A8 determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged, inputs BA0-BA2 select the bank. When all banks are to be precharged, inputs BA0-BA2 are treated as "Don't Care." Once a bank has been precharged, it is in the idle state and must be activated prior to any READ or WRITE commands being issued to that bank.
Figure 25: PRECHARGE Command
POWER-DOWN (CKE Not Active)
Unlike SDR SDRAMs, GDDR3 SDRAMs require CKE to be active at all times that an access is in progress: from the issuing of a READ or WRITE command until completion of the burst. For READs, a burst completion is defined when the Read Postamble is satisfied; For WRITEs, a burst completion is defined when the write postamble is satisfied. Power-down (shown in Figure26, Power-Down, on page38) is entered when CKE is registered low. If power-down occurs when all banks are idle, this mode is referred to as precharge power-down; if power-down occurs when there is a row active in any banks, this mode is referred to as active power-down. Entering power-down deactivates the input and output buffers, excluding CK, CK# and CKE. For maximum power savings, the user also has the option of disabling the DLL prior to entering power-down. In that case, the DLL must be enabled and reset after exiting powerdown, and 5K clock cycles must occur before a READ command can be issued. However, power-down duration is limited by the refresh requirements of the device, so in most applications, the self refresh mode is preferred over the DLL-disabled power-down mode. While in power-down, CKE LOW and a stable clock signal must be maintained at the inputs of the GDDR3 SDRAM, while all other input signals are "Don't Care." The power-down state is synchronously exited when CKE is registered HIGH (in conjunction with a NOP or DESELECT command). A valid executable command may be applied four clock cycles later.
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H5RS5223CFR Figure 26: Power-Down
Notes: 1~4; notes appear below table CKEn-1 L L L L H H H H NOTE: CKEn L L H H L L L H
Table 8: Truth Table - CKE
CURRENT STATE Power-Down Self Refresh Power-Down Self Refresh All Banks Idle Bank(s) Active All Banks Idle COMMANDn X X DESELECT or NOP DESELECT or NOP DESELECT or NOP DESELECT or NOP AUTO REFRESH See Truth Table 3 ACTIONn Maintain Power-Down Maintain Self Refresh Exit Power-Down Exit Self Refresh Precharge Power-Dwon Entry Active Power-Down Entry Self Refresh Entry 5 NOTES
1. CKEn is the logic state of CKE at clock edge n; CKEn-1 was the state of CKE at the previous clock edge. 2. Current state is the state of the GDDR3 SDRAM immediately prior to clock edge n. 3. COMMANDn is the command registered at clock edge n, and ACTIONn is a result of COMMANDn. 4. All states and sequences not shown are illegal or reserved. 5. DESELECT or NOP commands should be issued on any clock edges occurring during the tXSR period. A minimum of 5K clock cycles is needed for the DLL to lock before applying a READ command if the DLL was disabled.
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H5RS5223CFR
Notes: 1~3; notes appear below table CURRENT STATE Any CS# H L L Idle Row Active L L L L L Read (Auto Precharge Disabled) Write (Auto Precharge Disabled) L L L L L L RAS# X H L L L H H L H H L H H L
Table 9: Truth Table 3 - Current State Bank n - Command to Bank n
CAS# X H H L L L L H L L H L L H WE# X H H H L H L L H L L H L L COMMAND/ACTION DESELECT (NOP/continue previous operation) NO OPERATION (NOP/continue previous operation) ACTIVE (select and activate row) AUTO REFRESH LOAD MODE REGISTER READ (select column and start READ burst) WRITE (select column and start WRITE burst) PRECHARGE (deactivate row in bank or banks) READ (select column and start new READ burst) WRITE (select column and start WRITE burst) PRECHARGE (truncate READ burst , start Precharge) READ (select column and start READ burst) WRITE (select column and start new WRITE burst) PRECHARGE (truncate WRITE burst, start Precharge) 4 4 6 6 5 6 6, 8 5 6, 7 6 5, 7 NOTES
NOTE: 1. This table applies when CKEn-1 was HIGH and CKEn is HIGH (see Truth Table 2) and after tXSNR has been met (if the previous state was self refresh). 2. This table is bank-specific, except where noted (i.e., the current state is for a specific bank and the commands shown are those allowed to be issued to that bank when in that state). Exceptions are covered in the notes below. 3. Current state definitions: Idle: The bank has been precharged, and tRP has been met. Row Active: A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no register accesses are in progress. Read: A READ burst has been initiated, with auto precharge disabled. Write: A WRITE burst has been initiated, with auto precharge disabled. 4. The following states must not be interrupted by a command issued to the same bank. COMMAND INHIBIT or NOP commands, or allowable commands to the other bank should be issued on any clock edge occurring during these states. Allowable commands to the other bank are determined by its current state and Table9, and according to Table10. Precharging: Starts with registration of a PRECHARGE command and ends when tRP is met. Once tRP is met, the bank will be in the idle state. Row Activating: Starts with registration of an ACTIVE command and ends when tRCD is met. Once tRCD is met, the bank will be in the "row active" state. Read w/Auto-Precharge Enabled: Starts with registration of a READ command with auto precharge enabled and ends when tRP has been met. Once tRP is met, the bank will be in the idle state. Write w/Auto-Precharge Enabled: Starts with registration of a WRITE command with auto precharge enabled and ends when tRP has been met. Once tRP is met, the bank will be in the idle state. 5. The following states must not be interrupted by any executable command; COMMAND INHIBIT or NOP commands must be applied on each positive clock edge during these states. Refreshing: Starts with registration of an AUTO REFRESH command and ends when tRC is met. Once tRC is met, the GDDR3 x32 will be in the all banks idle state. Accessing Mode Register: Starts with registration of a LOAD MODE REGISTER command and ends when tMRD has been met. Once tMRD is met, the GDDR3 x32 will be in the all banks idle state. Precharging All: Starts with registration of a PRECHARGE ALL command and ends when tRP is met. Once tRP is met, all banks will be in the idle state. READ or WRITE: Starts with the registation of the ACTIVE command and ends the last valid data nibble. 6. All states and sequences not shown are illegal or reserved. 7. Not bank-specific; requires that all banks are idle, and bursts are not in progress. 8. May or may not be bank-specific; if multiple banks are to be precharged, each must be in a valid state for precharging. 9. Reads or Writes listed in the Command/Action column include Reads or Writes with auto precharge enabled and Reads or Writes with auto precharge disabled. 10. Requires appropriate DM masking. 11. A WRITE command may be applied after the completion of the READ burst
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H5RS5223CFR Table 10: Truth Table - Current State Bank n - Command to Bank m
Notes: 1~5; notes appear below table CURRENT STATE Any Idle Row Activating, Active, or Precharging Read (Auto Precharge Disabled) Write (Auto Precharge Disabled) Read(With Auto Precharge) Write(With Auto Precharge) CS# H L X L L L L L L L L L L L L L L L L L L L L NOTE: 1. This table applies when CKEn-1 was HIGH and CKEn is HIGH (see Table9) and after tXSNR has been met (if the previous state was self refresh). 2. This table describes alternate bank operation, except where noted (i.e., the current state is for bank n and the commands shown are those allowed to be issued to bank m, assuming that bank m is in such a state that the given command is allowable). Exceptions are covered in the notes below. 3. Current state definitions: Idle: The bank has been precharged, and tRP has been met. Row Active: A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no register accesses are in progress. Read: A READ burst has been initiated, with auto precharge disabled. Write: A WRITE burst has been initiated, with auto precharge disabled. Read with Auto Precharge Enabled: See following text Write with Auto Precharge Enabled: See following text RAS# X H X L H H L L H H L L H H L L H H L L H H L CAS# X H X H L L H H L L H H L L H H L L H H L L H WE# X H X H H L L H H L L H H L L H H L L H H L L COMMAND/ACTION DESELECT (NOP/continue previous operation) NO OPERATION (NOP/continue previous operation) Any Command Otherwise Allowed to Bank m ACTIVE (select and activate row) READ (select column and start READ burst) WRITE (select column and start WRITE burst) PRECHARGE ACTIVE (select and activate row) READ (select column and start new READ burst) WRITE (select column and start WRITE burst) PRECHARGE ACTIVE (select and activate row) READ (select column and start READ burst) WRITE (select column and start new WRITE burst) PRECHARGE ACTIVE (select and activate row) READ (select column and start new READ burst) WRITE (select column and start WRITE burst) PRECHARGE ACTIVE (select and activate row) READ (select column and start READ burst) WRITE (select column and start new WRITE burst) PRECHARGE 6 6 6 6 6, 7 6 6 6 6 6 NOTES
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H5RS5223CFR
3a. The read with auto precharge enabled or write with auto precharge enabled states can each be broken into two parts: the access period and the precharge period. For read with auto precharge, the precharge period is defined as if the same burst was executed with auto precharge disabled and then followed with the earliest possible PRECHARGE command that still accesses all of the data in the burst. For write with auto precharge, the precharge period begins when tWR ends, with tWR measured as if auto precharge was disabled. The access period starts with registration of the command and ends where the precharge period (or tRP) begins. During the precharge period of the read with auto precharge enabled or write with auto precharge enabled states, ACTIVE, PRECHARGE, READ and WRITE commands to the other bank may be applied. In either case, all other related limitations apply (e.g., contention between read data and write data must be avoided). 3b. The minimum delay from a READ or WRITE command with auto precharge enabled, to a command to a different bank is summarized below. 4. AUTO REFRESH and LOAD MODE REGISTER commands may only be issued when all banks are idle. 5. All states and sequences not shown are illegal or reserved. 6. READs or WRITEs listed in the Command/Action column include READs or WRITEs with auto precharge enabled and READs or WRITEs with auto precharge disabled. 7. Requires appropriate DM masking.
Table 11: Minimum Delay Between Commands to Different Banks with Auto Precharge Enabled
From Command To Command READ or READ with AUTO PRECHARGE WRITE with AUTO PRECHARGE WRITE or WRITE with AUTO PRECHARGE PRECHARGE ACTIVE READ or READ with AUTO PRECHARGE READ with AUTO PRECHARGE WRITE or WRITE with AUTO PRECHARGE PRECHARGE ACTIVE Minimum delay (with concurrent auto precharge) [WL + (BL/2)] tCK + tWTR (BL/2) tCK 1 tCK 1 tCK (BL/2) * tCK [CL + (BL/2) + 2 - WL] * tCK 1) 1 tCK 1 tCK
NOTE: CL = CAS latency (CL) rounded up to the next integer. BL = Burst length. WL = WRITE latency.
1) Write Data connot be driven onto the DQ bus for 2 clocks after the READ data is off the bus.(refer to Fig16. on the page29)
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H5RS5223CFR OPERATING CONDITIONS Absolute Maximum Ratings*
Voltage on Vdd Supply Relative to Vss .............................................-0.5V to +2.5V Voltage on VddQ Supply Relative to Vss .............................................-0.5V to +2.5V Voltage on Vref and Inputs Relative to Vss .............................................-0.5V to +2.5V Voltage on I/O Pins Relative to Vss ....................................-0.5V to VddQ +0.5V MAX Junction Temperature, TJ ...........................+125 Storage Temperature (plastic)................-55 to +150 Power Dissipation..........................................................TBD Short Circuit Output Current......................................50mA * Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Table 12: Thermal Characteristics
PARAMETER TC TJ Theta_JA Theta_JC Description Case Temperature Junction Temperature Thermal resistance junction to ambient Thermal resistance junction to case Value 115.0 126.2 47.8 9.0 UNIT NOTES 7 7
/W /W
1,2,3,4,5,7 1,2,6,7
Note: 1. Measurement procedures for each parameter must follow standard procedures defined in the current JEDEC JESD-51 standared. 2. Theta_JA and Theta_JC must be measured with the high effective thermal conductivity test board defined in JESD51-7 3. Airflow information must be deocumented for Theta_JA. 4. Theta_JA should only be used for comparing the thermal performance of signle packages and not for system related junction. 5. Theta_JA is the natural convection junction-to-ambient air thermal resistance measured in one cubic foot sealed enclosure as described in JESD-51. The environment is sometimes referred to as "still-air" although natural convection causes the air to move. 6. Theta_JC case surface is defined as the "outside surface of the package (case) closest to the chip mounting area when that same surface is properly hear sunk" so as to minimize temperature variation across that surface. 7. Test condition : Voltage 2.15V(Maximum voltage) / Frequency : 1.2Ghz
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H5RS5223CFR Table 13: DC Electrical Characteristics and Operating Conditions
(Recommended operating conditions; 0 <= TC <= 85 ) SYMBOL VDD/ VDDQ VREF VIH(DC) VIL(DC) II IOZ VOL(DC) MIN 1.95 Supply Voltage / I/O Supply Voltage I/O Reference Voltage Input High (Logic 1) Voltage Input Low (Logic 0) Voltage INPUT LEAKAGE CURRENT Any Input 0V <= Vin <= Vdd (All other pins not under test = 0V) OUTPUT LEAKAGE CURRENT (DQs are disabled; 0V <= Vout <= VddQ) OUTPUT Logic Low 1.7 1.455 0.69xVDDQ VREF+0.15 -5 -5 TYP 2.05 1.8 1.5 0.70xVDDQ MAX 2.15 2.15 1.545 0.71xVDDQ VREF-0.15 5 5 0.76 UNITS V V V V V V uA uA V Remark 1,5 2,5 3,5 4 PARAMETER/CONDITION
NOTE : 1. It supports 1G/1.2/1.3GHz speed at H5RS5223CFR-N0C/ N2C/N3C 2. It supports 500/700/900MHz speed at H5RS5223CFR-20C / 14C / 11C. 3. It supports 550/700MHz speed at H5RS5223CFR-18C / 14L. 4. VREF is expected to equal 70% of VDDQ for the transmitting device and to track variations in the DC level of the same. AC noise on VREF may not exceed +/- 2 percent of the DC value. 5. Under all conditions, VDDQ must be or equal to VDD.
Table 14: AC Input Operating
(Recommended operating conditions; 0 PARAMETER/CONDITION Input High (Logic 1) Voltage; DQ Input Low (Logic 0) Voltage; DQ Clock Input Differential Voltage; CK and CK# Clock Input Crossing Point Voltage; CK and CK# <= TC <= 85 ) SYMBOL VIH(AC) VIL(AC) Vid(AC) Vix(AC) MIN VREF+0.250 0.22 VREF-0.15 TYP MAX VREF-0.250 VDDQ+0.3 VREF+0.15 UNITS V V V V
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H5RS5223CFR OUTPUT IMPEDANCE AND TERMINATION DC ELECTRICAL CHARACTERISTICS
The Driver and Termination impedances are determined by applying VDDQ/2 nominal (0.9v) at the corresponding input or output and by measuring the current flowing into or out of the device. VDDQ is set to the nominal 1.8v.
* * * * * *
IOH is the current flowing out of DQ when the Pull-up transistor is activated and the DQ termination is disabled IOL is the current flowing out of DQ when the Pull-down transistor is activated and the DQ termination is disabled ITCAH(ZQ/2) is the current flowing out of the Termination of Commands and Addresses for a ZQ/2 termination value ITCAH(ZQ) is the current flowing out of the Termination of Commands and Addresses for a ZQ termination value. ITDQH(ZQ/4) is the current flowing out of the Termination of the DQs for a ZQ/4 termination value. ITDQH(ZQ/2) is the current flowing out of the Termination of the DQs for a ZQ/2 termination value
Note: Measurement performed with VDDQ = 1.8v (nominal) and by applying VDDQ/2 (0.9v) at the corresponding Input or Output. (0 Tc <= +85 )
<=
Table 15: Driver and Termination DC Characteristics (1.8V version)
200 PARAMETER ZQ VALUE MIN IOH IOL ITCAH (ZQ/2) ITCAH (ZQ) ITDQH (ZQ/4) ITDQH (ZQ/2) ZQ/6 ZQ/6 ZQ/2 ZQ ZQ/4 ZQ/2 24.5 24.5 8.2 4.1 16.4 8.2 MAX 30.0 30.0 10.0 5.0 18.0 10.0 MIN 20.5 20.5 6.8 3.4 13.6 6.8 MAX 25.0 25.0 8.3 4.2 16.7 8.3 MIN 17.5 17.5 5.8 11.7 11.7 5.8 MAX 21.4 21.4 7.1 14.3 14.3 7.1 UNITS mA mA mA mA mA mA NOTES 240 280 OHM
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45
H5RS5223CFR Figure 27: Input and Output Voltage Waveform
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46
H5RS5223CFR Table 16: Clock Input Operating Conditions (1.8V version)
PARAMETER/CONDITION Clock Input Midpoint Voltage; CK and CK# Clock Input Voltage Level; CK and CK# Clock Input Differential Voltage; CK and CK# Clock Input Differential Voltage; CK and CK# Clock Input Crossing Point Voltage; CK and CK# SYMBOL VMP(DC) VIN(DC) VID(DC) VID(AC) VIX(AC) MIN 1.16 0.42 0.22 0.22 VREF-0.15 0.70xVDDQ TYP 1.26 MAX 1.36 VDDQ+0.3 VDDQ VDDQ+0.3 VREF+0.15 UNITS V V V V V
Figure 28: Clock Input
NOTE: 1. This provides a minimum of 1.16V to a maximum of 1.36V, and is always 70% of VDDQ. 2. CK and CK# must cross in this region. 3. CK and CK# must meet at least VIN(DC) MIN when static and is centered around VMP(DC). 4. CK and CK# must have a minimum 600mV peak-to-peak swing. 5. CK or CK# may not be more positive than VDDQ + 0.5V or lower than 0.22V. 6. For AC operation, all DC clock requirements must also be satisfied. 7. Numbers in diagram reflect nominal values.
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H5RS5223CFR Table 17: Capacitance
Note: 13; notes appear on pages 52, 53 PARAMETER Delta Input/Output Capacitance: DQs, DQS, DM Delta Input Capacitance: Command and Address Delta Input Capacitance: CK, CK# Input/Output Capacitance: DQs, DQS, DM Input Capacitance: Command and Address Input Capacitance: CK, CK# Input Capacitance: CKE SYMBOL DCIO DCI1 DCI2 CIO CI1 CI2 CI3 MIN 1.5 1.0 1.0 1.0 MAX 0.20 0.40 0.10 3.5 3.0 3.0 3.0 UNITS pF pF pF pF pF pF pF NOTES 24 29 29
Table 18: IDD Specifications and Conditions (Units : mA)
Note:1-5, 10, 12, 14, 40; notes on page 52, 53; 0 PARAMETER/CONDITION OPERATING CURRENT: One bank; Active-Precharge; tRC (MIN); tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle; Address and control inputs changing once per clock cycle; WL=6 OPERATING CURRENT: One bank; Active Read Precharge; Burst = 4; tRC (MIN); tCK = tCK (MIN); Address and control inputs changing once per clock cycle; I(OUT) =0mA; WL=6 PRECHARGE POWER-DOWN STANDBY CURRENT: All banks idle; Power-down mode; tCK = tCK (MIN); CKE= LOW <= TC <= 85 SYMBOL MAX -18C -14L -20C -14C -11C -N0C -N2C -N3C NOTES
IDD0
140
160
160
200
240
300
350
400
22, 46
IDD1 IDD2P
140 30 60 40
160 40 80 50
160 60 80 60
200 70 100 70
240 80 120 80
300 90 170 100
350 110 250 150
400 130 300 180
22, 46 32
IDLE STANDBY CURRENT: CS# = HIGH; All banks idle; tCK = IDD2N tCK (MIN); CKE = HIGH; inputs changing once per clock cycle ACTIVE POWER-DOWN STANDBY CURRENT: One bank active; Power-down mode; tCK = tCK (MIN); CKE= LOW; WL=6 ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One bank; Active Precharge; tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle;WL=6 OPERATING CURRENT: Burst = 4; Reads; Continuous burst; One bank active; Address and control inputs changing once per clock cycle; tCK = tCK (MIN); I(OUT)=0mA; WL=6 OPERATING CURRENT: Burst = 4; Writes; Continuous burst; One bank active; Address and control inputs changing once per clock cycle; tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle; WL=6 AUTO REFRESH CURRENT tRFC (MIN) tRFC = 3.9us IDD3P
32
IDD3N
70
90
90
110
130
200
250
300
22
IDD4R
330
420
450
500
650
800
950
1050
IDD4W IDD5A IDD5B IDD6
330 230 70 10
420 250 90 10
450 250 80 20
500 300 110 20
650 350 130 20
800 400 200 25
950 500 250 25
1050 600 300 25 22 27 11
SELF REFRESH CURRENT: CKE <= 0.2V
NOTE : . `-18C/-14L' means low voltage so its current is measured at 1.545max voltage. . H5RS5223CFR-20C/-14C/-11C is standardized by 1.9max voltage. H5RS5223CFR-N0C/-N2C/-N3C is standardized by 2.1max voltage.
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H5RS5223CFR Table 19: Electrical Characteristics and AC Operating Conditions
Notes: 1-5,14-16,33,40; notes on pages52, 53; 0 AC Characteristics Parameter Parameter DQS out Access time from CK CK High-level width CK Low-level width Clock Cycle Time CL=9 CL=7 Symbol tDQSCK tCH tCL tCK tCK tWL tDH tDS tATS tATH tDQSH tDQSL tDQSQ tDQSS tDSS tDSH MIN -0.35 0.45 0.45 1.8 1,2,3,4, 5,6 0.25 0.25 10 10 0.48 0.48 -0.225 WL-0.2 0.25 0.25 tCL min or tCH min tHP0.225 0.3 0.3 0.5 0.5 1.3 4 0.52 0.52 +0.225 WL+0.2 <= TC <=85 -18C MAX +0.35 0.55 0.55 3.3 -14(L) MIN -0.26 0.45 0.45 1.4 1,2,3,4, 5,6 0.18 0.18 10 10 0.48 0.48 -0.160 WL-0.2 0.25 0.25 tCL min or tCH min tHP-0.16 0.3 0.3 0.35 0.35 1.0 6 0.52 0.52 +0.160 WL+0.2 MAX +0.26 0.55 0.55 3.3 Min -0.35 0.45 0.45 1.8 1,2,3,4, 5,6 0.25 0.25 10 10 0.48 0.48 -0.225 WL-0.2 0.25 0.25 tCL min or tCH min tHP0.225 0.3 0.3 0.5 0.5 1.3 4 0.52 0.52 +0.225 WL+0.2
-20C
Max +0.35 0.55 0.55 3.3
Unit tCK tCK tCK ns ns tCK ns ns ns ns tCK tCK ns tCK tCK tCK
Note
30 30 33, 40, 48 33, 40, 48 43 26, 31 26, 31
Write Latency DQ & DM input hold time relative to DQS DQ & DM input setup time relative to DQS Active termination setup time Active termination hold time DQS input high pulse width DQS input low pulse width DQS-DQ skew Write command to first DQS latching transition DQS falling edge to CK rising . setup time DQS falling edge from CK rising . hold time Half strobe period
25, 26
tHP
tCK
34
Data output hold time from DQS Data-out high-impedance window from CK/CK# Data-out low-impedance window fromCK/CK# Address and control input hold time Address and control input setup time Address and control input pulse width LOAD MODE REGISTER command cycle time
tQH tHZ tLZ tIH tIS tIPW tMRD
ns ns ns ns ns ns tCK 44 18 18 14 14
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H5RS5223CFR
AC Characteristics Parameter Parameter Average periodic refresh interval DQS read preamble DQS read postamble DQS write preamble DQS write preamble setup time DQS write postamble Jitter over 1~6 clock cycle error Cycle to cycle duty cycle error Rise and fall times of CK Symbol tREFI tRPRE tRPST tWPRE tWPRES tWPST tJ tDCERR tR, tF 0.4 0.4 0.4 0 0.4 MIN
-18C MAX 3.9 0.6 0.6 0.6
-14(L) MIN MAX 3.9 0.4 0.4 0.4 0 0.6 0.03 0.03 0.2 0.4 0.6 0.03 0.03 0.2 0.6 0.6 0.6 0.4 0.4 0.4 0 0.4 MIN
-20C
MAX 3.9 0.6 0.6 0.6
Unit us tCK tCK tCK ns
Note 23 46
20, 21 19, 37
0.6 0.03 0.03 0.2
tCK tCK tCK tCK
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H5RS5223CFR Table 19: Electrical Characteristics and AC Operating Conditions
Notes: 1-5,14-16,33,40; notes on pages 52, 53; 0 AC Characteristics Parameter Parameter DQS-out access time from CK CK High-level width CK Low-level width CL=11 Clock Cycle Time CL=11 CL=10 Write Latency DQ & DM input hold time relative to DQS DQ & DM input setup time relative to DQS Active termination setup time Active termination hold time DQS input high pulse width DQS input low pulse width DQS-DQ skew Write command to first DQS latching transition DQS falling edge to CK rising . setup time DQS falling edge from CK rising . hold time Half strobe period Symbol tDQSCK tCH tCL tCK tCK tCK tWL tDH tDS tATS tATH tDQSH tDQSL tDQSQ tDQSS tDSS tDSH MIN -0.22 0.45 0.45 1.1 1,2,3, 4,5,6 0.15 0.15 10 10 0.48 0.48 -0.13 WL-0.2 0.25 0.25 tCL min or tCH min tHP0.13 -0.3 -0.3 0.28 0.28 0.8 0.52 0.52 0.13 WL+0.2 -11C MAX +0.22 0.55 0.55 3.3 MIN -0.2 0.45 0.45 1 1,2,3, 4,5,6 0.13 0.13 10 10 0.48 0.48 -0.12 WL-0.2 0.25 0.25 tCL min or tCH min tHP-0.12 -0.3 -0.3 0.27 0.27 0.7 0.52 0.52 0.12 WL+0.2 <= TC <=85 -N0C MAX +0.2 0.55 0.55 2 Min -0.2 0.45 0.45 0.8 1,2,3, 4,5,6 0.125 0.125 10 10 0.48 0.48 -0.12 WL-0.2 0.25 0.25 tCL min or tCH min tHP-0.12 -0.3 -0.3 0.24 0.24 0.7 0.52 0.52 0.12 WL+0.2
-N2C
Max +0.2 0.55 0.55 2 Min -0.2 0.45 0.45 0.77 -
-N3C
Max +0.2 0.55 0.55 2 Unit Note
tCK tCK tCK ns ns ns tCK ns ns ns ns 30 30 33, 40, 48 33, 40, 48 33, 40, 48 43 26, 31 26, 31
1,2,3, 4,5,6 0.125 0.125 10 10 0.48 0.48 -0.12 WL-0.2 0.25 0.25 tCL min or tCH min tHP-0.12 -0.3 -0.3 0.23 0.23 0.7 0.52 0.52 0.12 WL+0.2
tCK tCK ns tCK tCK tCK 25, 26
tHP
tCK
34
Data output hold time from DQS Data-out high-impedance window from CK/CK# Data-out low-impedance window from CK/CK# Address and control input hold time Address and control input setup time Address and control input pulse width
tQH tHZ tLZ tIH tIS tIPW
ns ns ns ns ns ns 18 18 14 14
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H5RS5223CFR Table 19: Electrical Characteristics and AC Operating Conditions
Notes: 1-5,14-16,33,40; notes on pages52, 53; 0 AC Characteristics Parameter Parameter DQS read preamble LOAD MODE REGISTER command cycle time DQS read postamble DQS write preamble DQS write preamble setup time DQS write postamble Jitter over 1~6 clock cycle error Cycle to cycle duty cycle error Rise and fall times of CK Symbol tRPRE tMRD tRPST tWPRE tWPRES tWPST tJ tDCERR tR, tF MIN 0.4 7 0.4 0.4 0 0.4 0.6 0.03 0.03 0.2 0.6 0.6 <= TC <=85 N0C MAX 0.6 MIN 0.4 7 0.4 0.4 0 0.4 0.6 0.03 0.03 0.2 0.6 0.6 MAX 0.6 MIN 0.4 7 0.4 0.4 0 0.4 0.6 0.03 0.03 0.2 0.6 0.6 -N2C MAX 0.6 MIN 0.4 7 0.4 0.4 0 0.4 0.6 0.03 0.03 0.2 0.6 0.6 -N3C MAX 0.6 Unit tCK tCK tCK tCK ns tCK tCK tCK tCK 20, 21 19, 37 Note 46 44 -11C
VDDQ
Timing reference point
VDDQ 60
Data out
GDDR3
ZQ
10pF 240
AC timing reference load ( Refer to note3 on page52)
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H5RS5223CFR
Notes: 1. All voltages referenced to Vss. 2. Tests for AC timing, Idd, and electrical AC and DC characteristics may be conducted at nominal reference/supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified. 3. Outputs measured with equivalent load of 10pf terminated with 60 to VddQ. The output timing reference voltage level for single ended signals is the cross point with VREF (=0.7*VDDQ nominal). 4. AC timing and Idd tests may use a Vil-to-Vih swing of up to 1.0V in the test environment, but input timing is still referenced to Vref (or to the crossing point for CK/CK#), and parameter specifications are guaranteed for the specified AC input levels under normal use conditions. The minimum slew rate for the input signals used to test the device is 3V/ns in the range between Vil(AC) and Vih(AC). 5. The AC and DC input level specifications are a pseudo open drain design for improved high-speed signaling. 6. Vref is expected to equal 70 percent of VddQ for the transmitting device and to track variations in the DC level of the same. Peakto-peak noise on Vref may not exceed and an additional 25mV for AC noise. 7. Needed to further definitions. 8. Vid is the magnitude of the difference between the input level on CK and the input level on CK#. 9. The value of Vix is expected to equal 70 percent of VddQ for the transmitting device and must track variations in the DC level of the same. 10. Idd is dependent on output loading and cycle rates. Specified values are obtained with minimum cycle time at minium CAS latency and does not include the on-die termination current. Outputs are open during Idd measurements. 11. Enables on-chip refresh and address counters. 12. Idd specifications are tested after the device is properly initialized. 13. This parameter is sampled. Vdd = 1.8V, VddQ = 1.8V, Vref = Vss, f = 1 MHz, TA =25 , Vout(DC) = 0.75V, VddQ, Vout (peak to peak)= 0.2V. DM input is grouped with I/O pins, reflecting the fact that they are matched in loading. 14. Command/Address input slew rate = 3 V/ns. If the slew rate is less than 3 V/ns, timing is no longer referenced to the midpoint but to the Vil(AC) maximum and Vih(AC) minimum points. 15. The CK/CK# input reference level (for timing referenced to CK/CK#) is the point at which CK and CK# cross; the input reference level for signals other than CK/CK# is Vref. 16. Inputs are not recognized as valid until Vref stabilizes. Exception: during the period before Vref stabilizes, MF, CKE <= 0.3 x VddQ is recognized as LOW. 17. Not used in this Specification. 18. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referenced to a specific voltage level, but specify when the device output is no longer driving (HZ) or begins driving(LZ). 19. The maximum limit for this parameter is not a device limit. The device will operate with a greater value for this parameter, but system performance(bus turn-around) will degrade accordingly. 20. This is not a device limit. The device will operate with a negative value, but system performance could be degraded due to bus turnaround. 21. It is recommended that WDQS be valid (HIGH orLOW) on or before the WRITE command. 22. MIN (tRC or tRFC) for Idd measurements is the smallest multiple of tCK that meets the minimum absolute value for the respective parameter. tRASMAX for Idd measurements is the largest multiple of tCK that meets the maximum absolute value for tRAS. 23. The refresh period is 8K every 32ms. This equates to an average refresh rate of 3.9us. 24. The I/O capacitance per DQS and DQ byte/group will not differ by more than this maximum amount for any given device. 25. The valid data window is derived by achieving other specifications . tDQHP and tDQSQ. The data valid window derates in direct proportion to the strobe duty cycle and a practical data valid window can be derived. The strobe is allowed a maximum duty cycle variation of 48:52. Functionality is uncertain when operating beyond a 48:52 ratio. 26. Referenced to each output group: RDQS0 with DQ0.DQ7, RDQS1 with DQ8.DQ15, RDQS2 with DQ16.DQ23, and RDQS with DQ24.DQ31. 2 percent of the DC value. Thus, from 70% of VddQ, Vref is allowed 25mV for DC error
Rev.1.5 / Jul. 2008
53
H5RS5223CFR
27. This limit is actually a nominal value and does not result in a fail value. CKE is HIGH during REFRESH command period (tRFC [MIN]) else CKE is LOW (e.g., during standby). 28. The DC values define where the input slew rate requirements are imposed, and the input signal must not violate these levels in order to maintain a valid level. The inputs require the AC value to be achieved during signal transition edge, and the driver should achieve the same slew rate through the AC values. 29. The input capacitance per pin group will not differ by more than this maximum amount for any given device. 30. CK and CK# input slew rate must be >= 3 V/ns. 31. DQ and DM input slew rates must not deviate from WDQS by more than 10 percent. If the DQ/DM/WDQS slew rate is less than 3 V/ns, timing is no longer referenced to the midpoint but to the Vil(AC) maximum and Vih(AC) minimum points. 32. Vdd must not vary more than 4 percent if CKE is not active while any bank is active. 33. The clock is allowed up to during bank active. 35. For READs and WRITEs with auto precharge the GDDR3 device will hold off the internal PRECHARGE command until tRAS (MIN) has been satisfied. 36. The last rising edge of WDQS after the write postamble must be driven high by the controller.WDQS cannot be pulled high by the on-die termination alone. For the read postamble the GDDR3 will drive the last rising edge of the read postamble. 37. The voltage levels used are derived from the referenced test load. In practice, the voltage levels obtained from a properly termi nated bus will provide significantly different voltage values. 38. Vih overshoot: Vih (MAX) = VddQ + 0.5V for a pulse width <= 500ps and the pulse width cannot be greater than 1/3 of the cycle rate. Vil under-shoot: Vil (MIN) = 0.0V for a pulse width <= 500ps and the pulse width cannot be greater than 1/3 ofthe cycle rate. 39. The DLL must be reset when changing the frequency, followed by 5K clock cycles. 40. Junction temperature is a function of total device power dissipation and device mounting environment. Measured per SEMI G3887. 41. The thermal resistance data is based on a number of samples from multiple lots and should be viewed as a typical number. These parameters are not tested in production or just guaranteed by the simulation methods. 42. The WRITE latency can be set from 1 to 6 clocks but can never be less than 2ns for latencies of 1 and 3clocks. When the WRITE latency is set to 1 or 3 clocks,the input buffers are always on, reducing the latency but adding power. When the WRITE latency is set to 4 or 6 clocks the input buffers are turned on during the WRITE commands for lower power operation and can never be less than 7.5ns. 43. We'll try to cut these values for positive timing budget of 800MHz operations 44. Minimum of +9 cycles are needed to Read commands. 45. 8 Banks device sequential bank activation restriction: No more than 4 banks may be activated in a rolling tFAW(Four actvite wind ow). tFAW=4th Banks Act + tRRD*2=(tRRD*5). Converting to clocks is done by dividing tFAW by tCK and rounding up to next integer. 46. In here, tRPRE means, Low drive period of RDQS prior to the valid high rising edge. It doesn't include the High drive period prior to Low drive. 47. WR_A (write recovery time for autoprecharge) in clock cycles is calculated by dividing tWR (in nS) and rounding up to the next integer (WR[cycles] = tWR(ns)/tCK(ns)). The mode register must be programmed to this value. 48. tCK_max = 3.3ns at CL7~10, tCK_max = 2ns at CL11 90ps of jitter. Each timing parameter is allowed to vary by the same amount. 34. tHP (MIN) is the lesser of tDQSL minimum and tDQSH minimum actually applied to the device CK and CK# inputs, collectively
Rev.1.5 / Jul. 2008
54
H5RS5223CFR Table 20: Electrical Characteristics Usages as Clock phase
AC Characteristics Parameter
-18C
-16(L)*
-14(L)
-20C
-12C*
-11C
-N0C
-N2C
-N3C
Unit
Parameter
Symbol
MIN
MAX
MIN
MAX
MIN
MAX
Min
Max
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
ACTIVE to PRECHARGE command
tRAS
17
70Kns
19
70Kns
22
70Kns
15
70Kns
25
70Kns
28
70Kns
70Kns
28
70Kns
30
70Kns
tCK
ACTIVE to ACTIVE/AUTO REFRESH command period
tRC
24
-
28
-
31
-
22
-
35
-
40
-
-
39
-
42
-
tCK
AUTO REFRESH command period
tRFC
30
-
31
-
39
-
27
-
45
-
50
-
-
52
-
56
-
tCK
ACTIVE to READ delay
tRCDR
8
-
10
-
11
-
8
-
12
-
13
-
14
-
14
-
16
-
tCK
ACTIVE to WRITE delay
tRCDW
5
-
6
-
7
-
5
8
-
9
-
9
-
9
-
10
-
tCK
PRECHARGE command period
tRP
7
-
8
-
9
-
7
-
10
-
11
-
12
-
14
-
15
-
tCK
ACTIVE bank a to ACTIVE bank b command
tRRD
5
-
6
-
7
-
5
-
8
-
9
-
-
9
-
10
-
tCK
Bank active restriction rolling window
tFAW
28
-
32
-
35
-
25
-
40
-
44
-
48
-
48
-
48
-
tCK
Write recovery time
tWR
7
-
8
-
9
-
7
-
10
-
12
-
12
-
12
-
14
-
tCK
Internal WRITE to READ command delay
tWTR
4
-
5
-
6
-
4
-
7
-
8
-
-
7
-
7
-
tCK
WRITE recovery time + PRECHARGE command period
tDAL
14
-
16
-
18
-
14
-
20
-
22
-
24
-
26
-
29
-
tCK
Exit SELF REFRESH to READ command
tXSRD
5K
5K
5K
5K
5K
-
5K
-
5K
-
5K
-
5K
-
tCK
Exit self refresh to Non-Read command
tXSNR
300
-
300
-
300
-
300
-
300
-
300
-
300
-
300
-
300
-
tCK
Power-down exit time
tPDEX
4tCJK +tIS
5tCJK +tIS
5tCJK +tIS
4tCJK +tIS
6tCJK +tIS
-
7tCJK +tIS
-
7tCJK +tIS
-
7tCJK +tIS
-
7tCJK +tIS
-
tCK
Refresh interval time
tREF
-
3.9
-
3.9
-
3.9
-
3.9
-
3.9
-
3.9
-
3.9
-
3.9
-
3.9
us
Note) *: 1. It's only reference for customers who would like to use 700MHz(-14) part for 600MHz operation and 900MHz(-11) part of 800MHz operation and please use CL=8 for (-16) operation and CL=10 for (-12) operation. 2. `-18C/-14L' means low voltage so its value is measured at 1.545max voltage. 3. H5RS5223CFR-20C/-14C/-11C is standardized by 1.9max voltage and H5RS5223CFR-N0C/-N2C/-N3C is standardized by 2.10max voltage.
Rev.1.5 / Jul. 2008
55
H5RS5223CFR I/O and ODT Values
The Driver and Termination impedances are derived from the following test conditions under worst case process corners: 1. Nominal 1.8V (VDD/VDDQ) 2. Power the GDDR3 device and calibrate the output drivers and termination to eliminate process variation at 25 3. Reduce temperature to 10 4. Reduce temperature to 0 5. Raise temperature to 75 6. Raise temperature to 85 recalibrate. and take the fast corner measurement. and recalibrate and take the slow corner measurement .
I/O Impedances
Pull-Down Characteristic at 40 ohms Voltage (V) 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 MIN 2.144 4.268 6.373 8.449 10.505 12.542 14.540 16.509 18.449 20.341 22.203 24.017 25.783 27.480 29.119 30.671 31.387 31.648 MAX 3.366 6.516 9.454 12.185 14.715 17.051 19.400 21.828 24.219 26.580 28.913 31.222 33.508 35.813 38.213 40.551 42.900 45.176 Pull-Up Characteristic at 40ohms Voltage (V) 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 MIN -2.377 -4.705 -6.984 -9.283 -11.524 -13.803 -16.015 -18.285 -20.302 -22.223 -24.066 -25.773 -27.344 -28.683 -29.731 -30.691 -31.544 -32.311 MAX -2.946 -5.829 -8.644 -11.383 -14.038 -16.599 -19.051 -21.630 -24.143 -26.605 -29.005 -31.353 -33.619 -35.803 -37.883 -39.882 -42.003 -44.063
Rev.1.5 / Jul. 2008
56
H5RS5223CFR On Die Termination Values
Pull-Up Characteristic at 60ohms Voltage (V) 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 MIN -1.58 -3.14 -4.66 -6.19 -7.68 -9.20 -10.68 -12.19 -13.53 -14.82 -16.04 -17.18 -18.23 -19.12 -19.82 -20.46 -21.03 -21.54 MAX -1.96 -3.89 -5.76 -7.59 -9.36 -11.07 -12.70 -14.42 -16.10 -17.74 -19.34 -20.90 -22.41 -23.87 -25.26 -26.59 -28.00 -29.38 Pull-Up Characteristic at 120ohms Voltage (V) 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 MIN -0.79 -1.57 -2.33 -3.09 -3.84 -4.60 -5.34 -6.09 -6.77 -7.41 -8.02 -8.59 -9.11 -9.56 -9.91 -10.23 -10.51 -10.77 MAX -0.98 -1.94 -2.88 -3.79 -4.68 -5.53 -6.35 -7.21 -8.05 -8.87 -9.67 -10.45 -11.21 -11.93 -12.63 -13.29 -14.00 -14.69 Pull-Up Characteristic at 240ohms Voltage (V) 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 MIN -0.40 -0.78 -1.16 -1.55 -1.92 -2.30 -2.67 -3.05 -3.38 -3.70 -4.01 -4.30 -4.56 -4.78 -4.96 -5.12 -5.26 -5.39 MAX -0.49 -0.97 -1.44 -1.90 -2.34 -2.77 -3.18 -3.60 -4.02 -4.43 -4.83 -5.23 -5.60 -5.97 -6.31 -6.65 -7.00 -7.34
Rev.1.5 / Jul. 2008
57
H5RS5223CFR Figure 29: Data Output Timing - tDQSQ, tQH and Data Valid Window
NOTE: 1. tDQSQ represents the skew between the eight DQ lines and the respective RDQS pin. 2. tDQSQ is derived at each RDQS edge and is not cumulative over time and begins with first DQ transition and ends with the last valid transition of DQ. 3. tAC is shown in the nominal case. 4. tDQHP is the lesser of tDQSL or tDQSH strobe transition collectively when a bank is active. 5. The data valid window is derived for each RDQS transitions and is defined by tDV. 6. There are four RDQS pins for this device with RDQS0 in relation to DQ(0.7), RDQS1 in relation DQ(8.15), RDQS2 in relation to DQ(16.24), and RDQS3 in relation to DQ(25.31). 7. This diagram only represents one of the four byte lanes.
Rev.1.5 / Jul. 2008
58
H5RS5223CFR Figure 30: Data Output Timing - AC
NOTE: 1. tAC represents the relationship between DQ, RDQS to the crossing of CK and CK#.
Figure 31: Data Input Timing
NOTE: 1. tDSH (MIN) generally occurs during tDQSS (MIN). 2. tDSS (MIN) generally occurs during tDQSS (MAX).
Rev.1.5 / Jul. 2008
59
H5RS5223CFR
Package Information
Pin A1 Mark Pin A1 Mark
14

10
1.1 + 0.1 0.34+0.05
0.15+0.05 0.45+0.05 0.10 Max
Rev.1.5 / Jul. 2008
2-R0.13Max
2.0 12 11 10 9 4321
A B C D E F G H J K L M N P R T U
6
0.6
Unit:mm
60
H5RS5223CFR
Appendix A
The following diagram shows the general GDDR3 driver and terminator
Self Calibration flow for Driver and Terminator
First calibrate Pmos device against 240ohm resistor to VSS via ZQ pin This calibrate one Pmos leg to 240 ohms Use 1 Pmos leg for 240 ohm terminator Use 2 Pmos legs for 120 ohm terminator Use 4 Pmos legs for 60 ohm terminator Use 6 Pmos legs for 40 ohm pull up driver Next calibrate one Nmos leg against the already calibrated 240 ohm Pmos leg This calibrates one Nmos leg to 240 ohms Use 6Nmos legs for 40 ohm driver
Rev.1.5 / Jul. 2008
61
H5RS5223CFR
Apendix B Definition of Terminology
Hereafter are defined terminologies used in the GDDR3 SDRAM specification.
Although GDDR3 might be operated in ODT Disable Mode, it is not recommended and the specification describes the ODT Enable Mode only. Should a system be designed to operate the GDDR3 in ODT Disable Mode, the system should comprehend the effect of the discrepancies between this specification and its own design. If it is stated that a bus is in one of the following state, it should be interpreted as described.
Following are three terminologies defined for ODT Enable Mode.
- High{terminated}: A driver on the bus is driving the bus. One or more termination (ODT) on the bus is turned-on. The voltage level of the bus would be nominally VDDQ. - Hi-z{terminated}: No driver on the bus is driving the bus. One or more termination (ODT) on the bus is turned-on. The voltage level of the bus would be nominally VDDQ. - Low{terminated}: A driver on the bus is driving the bus. One or more termination (ODT) on the bus is turned-on. The voltage level of the bus would be nominally VOL(DC).
Corresponding terminologies for ODT Disable Mode are defined below.
As mentioned before, ODT Disable Mode is not an intended mode of operation. However, there exist situations where ODT Enable Mode can not be guaranteed for a short period of time, like during power up, yet is indeed an intended mode of operation. - High{unterminated}: A driver on the bus is driving the bus. No termination on the bus is active. The voltage level of the bus would be nominally VDDQ. - Hi-z{unterminated}: No driver on the bus is driving the bus. No termination on the bus is active. The voltage level of the bus would be undefined, because the bus would be floating. - Low{unterminated}: A driver on the bus is driving the bus. No termination on the bus is active. The voltage level of the bus would be nominally VSSQ.
Rev.1.5 / Jul. 2008
62
H5RS5223CFR
APPENDIX C Boundary Scan Test Mode
General Information
The 512Mb GDDR3 incorporates a modified boundary scan test mode as an optional feature. This mode doesn't operate in accordance with IEEE Standard 1149.11990. To save the current GDDR3 ballout, this mode will scan the parallel data input and output the scanned data through WDQS0 pin controlled by an addon pin, SEN which is located at V4 of 136 ball package.
Disabling the Scan feature
It is possible to operate the 512Mb GDDR3 without using the boundary scan feature. SEN(at V4 of 136ball package) should be tied LOW(VSS) to prevent the device from entering the boundary scan mode. The other pins which are used for scan mode, RES, MF, WDQS0 and CS# will be operating at normal GDDR3 functionalities when SEN is deasserted.
Figure C-1: Internal Block Diagram(Reference Only)
Rev.1.5 / Jul. 2008
63
H5RS5223CFR Table C-1: Boundary Scan (Exit) Order
BIT# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 Note: 1. When the device is in scan mode, the mirror function will be disabled and none of the pins are remapped. 2. Since the other input of the MUX for DM0 tied to GND, the device will output the continuous zeros after scanning a bit #67, if the chip stays in scan shift mode. 3. Two RFU balls (#56 and #57) in the scan order, will read as a logic"0". BALL D-3 C-2 C-3 B-2 B-3 A-4 B-10 B-11 C-10 C-11 D-10 D-11 E-10 F-10 E-11 G-10 F-11 PIN RDQ0 DQ2 DQ3 DQ0 DQ1 ZQ DQ9 DQ8 DQ11 DQ10 RDQ1 WDQS1 DM1 DQ13 DQ12 DQ15 DQ14 BIT# 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 BALL G-9 H-9 H-10 H-11 J-11 J-10 L-9 K-11 K-10 K-9 M-9 M-11 L-10 N-11 M-10 N-10 P-11 PIN BA1 WE# BA2 A5 CK CK# A7 A8 A6 A4 A9 DQ16 DQ17 DQ18 DQ19 DM2 WDQS2 BIT# 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 BALL P-10 R-11 R-10 T-11 T-10 T-3 T-2 R-3 R-2 P-3 P-2 N-3 M-3 N-2 L-3 M-2 M-4 PIN RDQS2 DQ20 DQ21 DQ22 DQ23 DQ31 DQ30 DQ29 DQ28 RDQS3 WDQS3 DM3 DQ27 DQ26 DQ25 DQ24 A3 BIT# 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 BALL K4 K-3 K-2 L-4 J-3 J-2 H-2 H-3 H-4 G-4 F-4 F-2 G-3 E-2 F-3 E-3 PIN A0 A2 A10 A11 RFU2 RFU1 A1 RAS# CKE BA0 CAS# DQ6 DQ7 DQ4 DQ5 DM0
Table C-2: Scan Pin Descriptions
BALL U-9 SYMBOL SSH Normal Funtion RES Type Input Descriptions Scan Shift. Capture the data input from the pad at logic LOW and shift the data on the chain at logic HIGH. Scan Clock. Not a true clock, could be a single pulse or series of pulses. All scan inputs will be referenced to rising edge of the scan clock. Scan Output. Scan Enable. Logic HIGH would enable the device into scan mode and will be disabled at logic LOW. Must be tied to GND when not in use. Scan Output Enable. Enables (registered LOW) and disables (registered HIGH) SOUT data. This pin will be tied to VDD or GND through a resistor (typically 1K) for normal operation. Tester needs to overdrive this pin to guarantee the required input logic level in scan mode.
F-9 D-2 U-4
SCK SOUT SEN
CS# WDQS0 RFU
Input Output Input
A-9
SOE#
MF
Input
Note: 1. When SEN is asserted, no commands are to be executed by the GDDR3. This applies both to user commands and manufacturing commands which may exist while RES is deasserted. 2. All scan functionalities are valid only after the appropriate power-up and initialization sequence. (RES and CKE, to set the ODT of the C/A) 3. In scan mode, the ODT for the address and control lines set to a nominal termination value of ZQ. The ODT for DQ's will be dis abled. It is not necessary for the termination to be calibrated. 4. During the power-up and initialization sequence, ZQ pin should be maintained the connection to VSSQ through proper RQ. 5. In a double-load clam-shell configuration, SEN will be asserted to both devices. Separate two SOE#'s should be provided to top and bottom devices to access the scanned output. When either of the devices is in scan mode, SOE# for the other device which is not in a scan will be disabled.
Rev.1.5 / Jul. 2008
64
H5RS5223CFR Table C-3: Scna DC Electrical Characteristics and Operating Conditions
Parameter/Conditionss Input High(Logic 1) Voltage Input Low(Logic 0) Voltage Note: 1. The parameter applies only when SEN is asserted. 2. All voltages referenced to GND. Symbol VIH(DC) VIL(DC) MIN VREF+0.15 MAX VREF-0.15 Units V V
Figure C-2: Scan Capture Timing
SCK
tSES
N o t a tr u e c l o c k, b u t a si n l g e p u l s e o r s e ri e s o f p u l s e s
SEN SSH
tSCS
SOE# Pins under Test
tSDS tSDH VALID DON'T CARE
Figure C-3: Scan Shift Timing
SCK
tSES
SEN
tSCS
SSH
tSCS
SOE# SOUT
tSAC Scan Out bit 0 tSOH Scan Out bit 1 Scan Out bit 2 Scan Out bit 3
Transitioning Data
Rev.1.5 / Jul. 2008
65
H5RS5223CFR Table C-4: Scan AC Electrical Charateristics
Parameters/Conditions Clock Clock Cycle time Scan Command Time Scan enable setup time Scan enable hold time Scan command setup time for SSH, SOE# and SOUT Scan command hold time for SSH, SOE# and SOUT Scan Capture Time Scan capture setup time Scan capture hold time Scan Shift Time Scan clock to valid scan output Scan clock to scan output hold tSAC tSOH 1.5 6 nS nS 1 1 tSDS tSDH 10 10 nS nS 1 1 tSES tSEH tSCS tSCH 20 20 14 14 nS nS nS nS 1,2 1 1 1 tSCK 40 nS 1 SYMBOL MIN MAX UNITS NOTE
Note: 1. The parameter applies only when SEN is asserted. 2. Scan Enable should be issued earlier than other Scan Commands by 10nS.
Figure C-4: Scan Initialization Sequence
VDD VDDQ VREF RES (SSH) CKE SEN SCK SOE# SOUT PUT
T=200S T=200S RESET at Power-up Boundary Scan Test Mode tSCS tSCS tSCS tATS tATH tSDS tSCH tSDH tSCS tSCH tSCH
VALID
tSES
tSDS
tSDH
VALID
Power-up: VDD Stable
DON'T CARE
Note: To set the pre-defined ODT for C/A, a boundary scan mode should be issued after an appropriate ODT initialization sequence with RES and CKE signals
Rev.1.5 / Jul. 2008
66

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